管理層發言
Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's First Quarter Fiscal 26 Earnings Results Conference Call. As a reminder, today's call is being recorded for replay purposes. I would now like to turn the conference over to Ms. Alison Ziegler, of Darrow Associates. Ms. Ziegler, you may proceed.
Thank you, Sherry, and thanks to all of you for joining us. Our speakers today are Brian C. Faith, President and Chief Executive Officer and Elias N. Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing and payments related to our government contract, statements regarding the expected magnitude of potential contracts, and statements regarding the expected adoption rates and/or orders by our customers. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply or delivery of, or demand for, the company's products and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions of the risks, uncertainties, and assumptions that could result in these differences please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current historical non-GAAP data. Please note QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR page shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.
Thank you, Alison. Good afternoon, everyone, and thank you all for joining our first quarter 26 conference call. Since our last conference call, we have made significant progress toward our goal of delivering 50% to 100% year-over-year revenue growth in 2026. With this, we continue to expect our storefront and our new RadPro FPGA will contribute to our anticipated revenue growth and second-half profitability. As we announced in an April 9 press release, we introduced and demonstrated our new RadPro FPGA and development kit at the Hardened Electronics and Radiation Technology, or HART, conference last month. HART is a highly specialized conference where attendees must show proof of U.S. citizenship, and their affiliation with a company or academia that is certified through the joint certification program. RadPro is our trademarked brand for radiation-hardened FPGAs. The test chip we demonstrated at the HART conference with our RadPro dev kit was internally funded and is independent of our U.S. government contract. These test chips were fabricated on the GlobalFoundries 12LP process which is the same process used by many defense industrial base (DIBs) for radiation-hardened ASICs. This means that in addition to successfully demonstrating our new discrete RadPro FPGA, we have also illustrated our capability to support requirements for eFPGA and radiation-hardened ASICs and SoCs fabricated on the GlobalFoundries 12LP process. Our demonstrations and meetings at HART with leading DIBs went very well and we have since shipped multiple RadPro dev kits. These shipments will provide a low six-figure contribution to our Q2 revenue. While we expect it will take until 2026 for DIBs to fully evaluate our new RadPro FPGA, we have already signed an MOU with one DIB to accelerate the mutual evaluation of a potential RadPro chiplet application. In addition to the progress we have made with our RadPro FPGA, in a March 17 press release, we announced our fourth contract targeting Intel 18A technology. While these initial contracts have been smaller, their total value is now nearly $2 million, and together they are the framework for the larger contracts we expect to book later this year. The first two contracts were for Intel 18A test chips. We anticipate receiving our test chip allocation from the first contract later this quarter. We believe the data we gather from our evaluation of these test chips will enhance our ability to win new production contracts. The third contract was for a 1 million LUT feasibility study which led us to implement some notable architectural enhancements that we can leverage across all advanced fabrication nodes. With these architectural enhancements in place, we can address the lucrative markets that require very high density eFPGA cores and ASIC designs, and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including chiplets and a variety of storefront opportunities. The fourth and most recent contract leverages the architectural enhancements that were developed during the 1 million LUT feasibility study. In support of this contract, we will deliver hard IP for a very large Intel 18A eFPGA core in support of our customers' ASIC design. The test chip for this ASIC design is targeted for tape-out during the second half of 2026. We anticipate a fifth mid-six-figure contract from this customer during 2026 that further extends our work on very high density architecture. The timing of funding remains uncertain; our discussions with this DIB have expanded to include the potential of QuickLogic providing storefront services for a customer-designed ASIC that will include our eFPGA hard IP. We expect to learn more about the potential expansion to storefront services and the timing of this possible award in the coming months. In addition to these DIB contracts, we are working closely with a large commercial customer on a contract based on Intel 18A valued at several million dollars. In our last conference call, I said that I expected this contract would be awarded in late Q2. However, the customer is evaluating an expansion in the size and function of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, we are now forecasting this contract to be awarded during Q3. On December 8, we issued a press release announcing Idaho Scientific selected our eFPGA hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile IoT, infrastructure, and defense systems applications. We are continuing to support the integration of our hard IP into its tape-out, which is anticipated next year. Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA hard IP into its secure system-on-chip processors, Idaho Scientific can further enhance its cryptographic security and address new markets much more quickly with lower risks and lower costs. Since our last conference call, Idaho Scientific has been fully integrated with General Dynamics Mission Systems. We believe this integration may lead to new opportunities for QuickLogic. Last year, we announced an eFPGA hard IP contract with a new defense industrial base customer valued at $1.1 million that will be fabricated on the GF 12LP process. This application utilizes a large block of our eFPGA hard IP for critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes. With the cooperation of this DIB and its end customer, we have leveraged the large eFPGA core to win a new seven-figure contract that was finalized last week and will contribute to Q2 revenue. The delay of this award is why our Q1 revenue was below the midpoint of our guidance. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA hard IP in an ASIC. In parallel with these efforts, we are exploring the potential to leverage the FPGA from this contract as a storefront chiplet. We are already seeing interest from some of our partners on this concept. Due largely to the strategic initiatives we launched in 2025, we believe we are building meaningful traction in the chiplet markets. We are currently working on numerous proposals at various stages that include direct U.S. government, DIB, and commercial applications. These proposals include opportunities targeting several fabrication processes including GlobalFoundries 12LP and Intel 18A. Last year, the commercial chiplet ecosystem was mired in debate regarding the communications and protocol layers. In response, we introduced the first phase of our digital proof-of-concept chiplet program as a strategy to move forward prior to customer commitments and, with that, accelerate our storefront chiplet initiatives. Internally, we refer to this as POC. With the support of our large strategic partners, we leveraged our existing eFPGA hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. We presented a paper on the POC at the Chiplet Summit in mid-February and gave a presentation with Intel Foundry at an event at the Government Microcircuit Applications and Critical Technology, or GOMAC Tech Conference, in March. As a reminder, QuickLogic is a member of the Intel Foundry Accelerator Ecosystem Alliance program participating in the chiplet, IP, and USMAG alliances. In our last conference call, I stated that the net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. This opinion was bolstered at the GOMAC Tech Conference. The primary hurdles today are interoperability gaps and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge. With that, I will turn the call over to Elias for his presentation of financial data.
Thank you, Brian. Good afternoon, everyone. Total first quarter revenue was $5.1 million. This was up 16.5% from Q1 2025 and up 35.3% from Q4 2025. Revenue was $450 thousand below the midpoint of our guidance due to a delay in the award of a certain contract that we finalized last week. Revenue recognition for this contract would be ratable and will now extend through Q1 27 versus through Q4 26. This shift forward in revenue recognition does not impact the full year revenue outlook that Brian shared earlier. New product revenue in Q1 was $4.3 million and mature product revenue was $800 thousand. New product revenue was up 14.2% from Q1 2025, and up 50.7% compared to Q4 2025. Mature product revenue was up 31.7% compared to Q1 2025 and down 14.2% from Q4 2025. Non-GAAP gross margin in Q1 was 39.6%. This was below our outlook of 45% plus or minus 5%. The shortfall was due to inventory reserves of about $300 thousand, $198 thousand. This compares to 45.7% in Q1 2025 and 20.8% in Q4 2025. Non-GAAP operating expenses in Q1 were $3.3 million. This compares to $3 million in Q1 2025 and $3.5 million in Q4 2025. Q1 26 non-GAAP net loss was $1.3 million or a loss of $0.08 per share. This compares to a non-GAAP net loss of $1.1 million or loss of $0.07 per share in Q1 2025 and a non-GAAP net loss of $2.8 million or loss of $0.17 per share in Q4 2025. The difference between our GAAP and non-GAAP results is mainly related to non-cash stock-based compensation expenses. Stock-based compensation for Q1 was $858 thousand compared to $904 thousand in Q1 2025 and $744 thousand in Q4 2025. Restructuring costs were $11 thousand in Q1 26 compared with $141 thousand in Q1 2025 and zero in Q4 2025. For the first quarter, two customers accounted for 10% or more of total revenue. At the close of Q1, net cash was $6 million. This compares with $3.8 million in net cash at the close of Q4 2025. This increase of $2.2 million in net cash is inclusive of $3.2 million raised with our ATM during Q1 2026. Now moving to our guidance and our outlook for our second fiscal quarter, which will end on 06/28/2026. Based on backlog and customer forecast, our total revenue guidance for Q2 is $6 million plus or minus 10%. We expect total revenue to be comprised of $5.2 million in new product revenue, and $800 thousand in mature product revenue. We anticipate an increase in mature product revenue during the second half that drives the full year total to approximately $4 million. Based on the anticipated Q2 revenue mix, non-GAAP gross margin for the second quarter is expected to be approximately 42% plus or minus 5%. As I noted in our last conference call, there are several factors weighing on our non-GAAP gross profit margin during 2026. For the full year, we are still modeling a non-GAAP gross profit margin of approximately 57%. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. These classifications are related to labor and tooling for IP contracts. This may cause variability in our quarterly gross margins and operating expenses that will usually balance out on the operating line. With that in mind, our Q2 non-GAAP operating expenses are expected to be $3.3 million plus or minus 5%. We are still expecting full year non-GAAP operating expenses to be approximately $13.5 million. This forecasted growth of approximately 14% in non-GAAP OpEx over 2025 is to support our anticipated 50% to 100% revenue growth in 2026 that Brian mentioned earlier. After interest and other income, we are forecasting a Q2 net loss of about $800 thousand or loss of approximately $0.04 per share. Based on our current outlook, we anticipate non-GAAP profitability for 2026. The main difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses. In Q2, we expect this compensation to be approximately $900 thousand which is similar to Q1 26 and Q2 25. As a reminder, there will be movement in stock-based compensation during the year and it may vary quarter to quarter based on the timing of grants. We raised approximately $6.4 million in net proceeds during Q1 2026 using our existing ATM. Based on our current outlook, we do not anticipate further sales using our existing ATM during the balance of fiscal 2026. Excluding money raised with our ATM, we anticipate Q2 cash use of approximately $500 thousand. Inclusive of money raised with our ATM, we anticipate closing Q2 with just under $12 million in net cash. Please note that our cash used could vary based on the timing of certain payments and receipts from contracts during the quarter. Based on our current outlook, we anticipate positive cash flow during 2026. As reported in our 8-K filed on 04/30/2026, we have secured a new banking partner. With this new agreement, and considering the amount we have raised with the ATM, we intentionally lowered our credit line to $10 million and secured more favorable terms that will lower our borrowing costs. I want to thank you for your time. With that, I will now turn the call over to Brian for his closing comments.
Thank you, Elias. The entire QuickLogic team has worked very hard to accomplish numerous tangible milestones that have set the stage well for 2026 and beyond. This execution along with the strategic investments and strong customer alliances, are the driving forces for the revenue growth we are forecasting to begin this year. The most significant investments have been our development of eFPGA hard IP for Intel 18A technology, and the tape-out of our first RadPro FPGA test chip. These internally funded investments have provided us with unique positioning in the market and have enabled us to develop close alliances with strategic customers that we believe will benefit QuickLogic for years to come. With our first RadPro FPGA in hand, we have already received numerous orders for our RadPro dev kits for evaluation revenue. The shipment of these dev kits will make a low six-figure contribution to our Q2 revenue. This positions us very well to address applications for various levels of radiation-hardened discrete FPGAs and eFPGA hard IP for customer ASIC and SoC designs. Our early investments to become the first, and as it stands today only, company to offer eFPGA hard IP for Intel 18A has also enabled us to build strong customer alliances. One of these customers has already awarded us four contracts with a fifth anticipated during 2026. Through these contracts, we expect to receive our allotment of test chips that will enable us to fully characterize the performance of our eFPGA hard IP on Intel 18A. With these data in hand, I believe we can accelerate new contract awards for DIB and commercial applications. This customer also funded the 1 million LUT Intel 18A feasibility study that led us to implement a number of architectural enhancements. These enhancements have expanded our SAM to include the lucrative markets for very high density discrete FPGAs and eFPGA hard IP blocks in ASIC and SoC designs. In addition to the many initiatives I have outlined today that are designed to power our long-term growth, we are planning three multi-project wafer or MPW tape-outs this year. All three tape-outs are for chips that we intend to sell via our storefront program. And as I mentioned earlier, the cost for two of these tape-outs will be fully covered by customer contracts that are already on the books. We believe the third tape-out will be covered at least in part by a customer contract. Our strong outlook for 2026 is based largely on the foundation we built during the preceding years. As I hope we have articulated well during this call, the QuickLogic team is intensely focused on the continued execution of the strategic milestones that we believe will fuel our growth and profitability for years to come. With that, we will now open the call for questions.
分析師問答
Thank you. If you would like to ask a question, please press *1 on your telephone keypad. A confirmation tone will indicate your line is in the question queue. You may press *2 if you would like to remove your question from the queue. Our first question is from Richard Shannon with Craig-Hallum Capital Group. Please proceed.
Well, great. Thanks, Brian and Elias, for taking my questions. Apologies. I am in transit. Hopefully, the ambient noise is not too bad here. Oh, no problem. Let's see. I guess my first question, Brian, is you talked about your customers that are ordering and taking in the test chips, I think called the RadPro dev kit here. They are going to take most of the year to do this. I just want to make sure that that is well within the timing to hit some key programs. I am sure these are intended for. I just want to get some assurance if that is not at risk in any way.
Yeah. Richard, we have modeled out some of these key programs that, you know, we have been designing this chip for from day one, and it aligns well with those. I will remind everybody that is why we actually invested in funding our own test chip: to make sure that we did tape-outs in time and test kits to meet within that evaluation window. And we feel like we are within that window. We're thrilled to see the uptake of both the orders and the requests for pricing and lead times of the dev kits coming out of the HART conference.
Okay. What do you expect to be the next steps with these customers? Just help us understand what to expect next. What are those milestones to look for?
I mean, there are numerous milestones to get to getting designed into an architecture, but I think from an outward-facing milestones that we can talk about, throughout this year people will be doing their own functional evaluation of the tools and the devices, perhaps their own radiation testing, along with us doing that. And then, like I said on the call, about by the end of the year timeframe is when we expect to start getting some feedback from people on interest in designing us into these architectures for hopefully programs of record and even ones that are not out there yet. That lines up well with what we think will be the schedule for our next chips coming off this whole initiative. And we are tracking those schedules very detailed, as you can imagine, to line up architecture finish and the need for new silicon in the 2027 timeframe.
Okay, that is good to hear. Thanks for that update, Brian. I wanted to ask a question on Intel 18A here. Sounds like you are having great progress with one particular customer I think it is a DIB here. I guess I would love to get a sense of what kind of breadth you are expecting or hoping to see in that node, which I understand is being promoted broadly by the U.S. government to the DIBs here. We have heard a lot about one customer. Do we expect to see any more here? What is kind of the pipeline for, you know, expansion with Intel?
Yeah. We are actually tracking a handful of opportunities at different customers, not just this first one. Some of them are looking at the developments that we are doing and some of these architectural enhancements and assessing how they might use that to benefit from those enhancements as well for larger density. Some of the opportunities could be using our smaller-density architecture today. So we have several. Like I said, it is a handful. So I think we are going to expand on that at some point this year. And I have said this publicly, I will reiterate it here: it is not just the defense industrial base that is looking at Intel 18A. From our perspective for eFPGA, it is actually into the commercial side. So we are targeting a commercial win this year as well for our IP on that note.
That is good to hear, Brian. Thanks for that. Let's see. Unless I missed something here, I did not hear any comments specifically about the revenue growth profile you mentioned in the last earnings call for this year — that being 50% to 100% type. If you did, I apologize for that. But just want to get an update thought process, and how, you know, what the profile of the year looks like given the guidance here. Unfortunately, I have not been able to update my models, so I do not have an overly intelligent way of asking this question. But if you could just kind of give me the top down about how you are going to approach that. Are you thinking of anything meaningfully towards the low end or high end of that number?
No. In fact, the first sentence I said after welcoming everybody was the progress we have made towards delivering on that 50% to 100% revenue growth target for the year. And if you think about what we did in Q1 plus our guide for Q2, that is already 80% of last year just in the $11 million in the first half versus $13 million-something last year. So I think we are making really good progress on that. Really on all fronts on the IP side with 18A. Thrilled to get the test chips and dev kits out for the RadPro FPGA because that is a huge uplift there. And then also just on some of these new proposals we talked about earlier on different chiplet initiatives, storefront initiatives, and then bolstered by some of our mature business being stronger in the second half than the first half. So we are feeling good about being in that range that we talked about entering the year.
Okay. Perfect. Thanks for doing all that math for me. I will do that offline and ask some better questions later, but thanks for that, Brian. Last question, probably for Elias here on gross margins. What are the dynamics driving the gross margins from, I think, kind of the low-40s range here to the 57% for the year. That implies pretty healthy levels for the second half. Just want to get a sense of the dynamics driving that, Elias, and that is all for me.
Yeah. As you know Richard, I have said this so many times; it is the most difficult one to teach. The gross margin in this company moves up and down and is different by quarter, but the way I am looking at it is that there is going to be more higher gross margin mix in the second half than in the first half. For example, certain professional services bring in lesser gross margin than the IP or the product itself that you are selling. So as you increase product and IP in the second half, to Brian's point that we are going to have $13 million-something in the second half, that gives you the comfort that the gross margin should be up there. I still want to shoot for 57%. Now if it comes at 55%, nobody should shoot arrows at me. But I mean, that is a pretty good bump from last year. I will take that into account and adjust accordingly.
Our next question is from Tyler Burmeister with Lake Street Capital Markets. Please proceed.
Hey, guys. Thanks for letting us ask a couple of questions here. I guess I wanted to ask maybe on the U.S. government strategic radiation hardening program. You received the $13 million last tranche in the last year, beginning of this year. Any updated thoughts on potential for additional funding tranches from that program later this year?
Yeah. Definitely. So we had talked previously — I think I have shared publicly — that $13 million tranche we are expecting to fully recognize this year. We are continuing our developments of these next chips. And I think you could assume that we would probably be getting another contract by the end of the year to continue that even further into 2027 and to round out the necessary things to complete it.
I guess that kind of already answered my next question. But then that would, I think, imply that the final chip design with that program remains on track for later this year?
I wish I could share more programmatic details on that. I am not allowed to, so I am not going to do that here, but let me say we are comfortable with the way we are executing.
Alright. And then maybe pivoting over to your RadPro development kits. I think you said several of them have shipped so far. Is that with one customer or multiple customers? Any way to maybe think about the diversity of the customers so far?
It is multiple. Let's start with that. And I would say the frequency of inbound interest for it has picked up now that we have been able to talk more about it in forums that matter like the HART conference. There is a slew of these government, defense, radiation-oriented type conferences. They tend to be a little bit more boutique in nature than something like DAC or Embedded Systems, but the quality of leads that we engage with there is high because it is very focused. Coming out of HART, there is a lot of interest for the dev kits. We are going through that now. We even got messages today from people saying, 'Hey, we are interested; what is the lead time and the cost like?' So I think we are going to continue to ship these throughout the year, which is great because that is a leading indicator of interest and it gets our software and devices into the hands of these customers. We want to see engineering resources working with our technology.
I appreciate that color. Maybe last one for me. You explained well the one contract push-out from Q1 to Q2 and reiterated the full year to be 50% to 100%. One quarter through the year, that is still a decent range. Is it possible to call out maybe the couple biggest potential drivers that could swing that from the low end to the high end — is it really just potential timing across the board?
Well, I guess the way I was answering that first question from Richard on the revenue for the year and how it fills in — with $11 million in the first half, like I said, that is 80% of last year. So I think we are well on our way to getting into the 50% to 100% range. As far as components of that growth, one is the continued execution on the government contract, which I already alluded to and we feel good about. Another was entering the year to be shipping these dev kits for the 18A — the embedded FPGA hard IP. One of our customers that I mentioned has already had multiple contracts with us and getting this next one for the second half is something that has to be done still, but we are feeling good about that. We do have a larger 18A IP contract in the forecast for the year, a real commercial contract. To the extent you guys are tracking press, that would be that commercial customer I am talking about for Intel 18A eFPGA IP. That would be one that we need to close to be into the upper end of the forecast range. Like I said, I think we are feeling good about it. It felt great to finally get the one we signed last week — that was a good milestone because that was a fairly large amount of revenue that we are forecasting for the year, just a quarter later, but good to get it on the books and start executing. So not too many more deals to sign to get into the upper half of that range we talked about.
That sounds great. I appreciate that color as well. That is all from me, guys. Thanks.
Our next question is from Neil Young with Needham and Company. Please proceed.
Hey, everyone. Thank you for letting me ask some questions. Wanted to start asking on storefront here. So as storefront begins to scale, how should we think about the financial profile? More specifically, should storefront carry a meaningfully different gross margin or revenue recognition pattern once you move from the dev kits and test chips into more of a repeatable product shipments?
Yeah. I can take that one. So storefront is just like the classic semiconductor device business. We run the supply chain; we sell the device to the customer. It is revenue and a gross margin at that point in time. Very little R&D goes on top of that because the devices are effectively done. So the gross margin, yes, will be higher. For modeling, historically you would expect devices like this to be mid- to high-60s percent margin. It is more predictable and less up and down because it is less to do with services and much more to do with just shipping a product. Revenue is recognized as it goes out the door and gross margin at that point in time because we know the cost of goods. It is much more predictable.
Thanks. And then I wanted to ask on Quantum Leap Solutions. I know you appointed them as authorized sales rep for IP and chiplet offerings. How should we think about the role of that channel in accelerating customer acquisitions? Should we think about the bigger opportunities revolving around opening new commercial accounts, deepening the defense and aerospace engagement, helping customers navigate chiplet and ASIC integration decisions earlier in the design cycle? Any color would be helpful. Thanks.
Yeah. As a company of our size, most semiconductor companies have a direct sales force and then an external sales force or indirect. Indirect is usually distributors or sales reps. In the case of design-in products, where you have to get in early into the architecture, you want sales reps that are focused on that type of technology. For us, that could be semiconductor IP, EDA tools — all of this stuff that ASIC teams typically use because our sales rep knows those ASIC design groups. They have established rapport and trust and can expose those groups to QuickLogic technology. They are not just defense; they also do a lot of commercial. I think they have a pretty strong background in helping sell EDA tools, which is great because every ASIC design team that needs IP needs EDA tools. So they know the right people to go to. That really helps give us leverage for our operating model because most sales reps and distributors are success-based: they get a commission or margin on the sale. So it is a fantastic way of aligning what we need as a company with financial incentives for them. I think they are doing a great job getting us into groups that are beyond what we could handle with just our direct sales force today.
Yeah. Thank you. Great.
As a reminder, just press *1 on your telephone keypad if you would like to ask a question. We will pause for a brief moment to see if there are any final questions. With no further questions at this time, I would like to turn the floor back over to Brian for closing remarks.
Thank you all for joining and participating today. We look forward to speaking with you in the near future or on our next earnings call in August, whichever comes sooner. Thank you.
Thank you. This will conclude today's conference. You may disconnect at this time, and thank you for your participation.